1. Field of the Invention
The present invention relates to integrated circuits and more particularly to the protection of integrated circuits against so-called “latch-up” phenomena.
It applies mainly, but not exclusively, to CMOS-type (Complementary Metal-Oxide Semiconductor) integrated circuit technologies that are particularly sensitive to this phenomenon.
2. Description of the Related Art
The latch-up phenomenon manifests itself in an inrush current linked to the triggering of a parasitic thyristor structure inherent in certain integrated circuit technologies, and in particular in the CMOS-type technologies.
The MOS transistor-based architectures have parasitic bipolar transistors the gain of which can be very high (50 to 100). Therefore, the parasitic transistors do not disrupt the operation of the circuit, except in certain parasitic thyristor-type configurations (PNPN) in which two parasitic bipolar transistors work in positive feedback, forming a bistable configuration which can be triggered by slight disturbance. Once the feedback is established, the thyristor is in a high conduction state that powers itself even after the disappearance of the disturbance, due to the fact that the thyristor is placed directly in parallel on the power supply. This state can therefore prove destructive for the integrated circuit.
Such a parasitic thyristor configuration is shown in FIG. 1 that represents in a cross-section the structure of a CMOS integrated circuit cell, comprising for example a logic gate such as an inverter.
The integrated circuit IC cell represented in FIG. 1, of P-substrate and N-well type, comprises two N- and P-channel MOS transistors, produced in a P−-doped semi-conductive substrate 1. The P-channel MOS transistor is formed in an N−-doped region 2 of the substrate, referred to as a “well”. The well comprises a drain region 3, a source region 4, these regions being P+ doped, and an N+-doped region 5. The regions 3, 4 that delimit the channel of the P-channel MOS transistor, are respectively connected to an output 10 of the cell and to the supply terminal Vdd. The region 5 receives the supply voltage Vdd. The N-channel MOS transistor is formed in the substrate 1 by a source region 7, a drain region 8, these regions being N+-doped and delimiting the channel of the N-channel MOS transistor, and a P+-doped region 6 connected to the ground. The regions 7, 8 are respectively connected to the ground terminal and to the output 10 of the cell.
Layers 9, for example in polysilicon, formed above the channels N and P of the two transistors, constitute the gates thereof and are connected to the input 11 of the integrated circuit cell.
FIG. 1 also represents, in thinner lines, the position of the parasitic thyristor in relation to the doped regions forming the two transistors MOS. The parasitic thyristor is formed by two bipolar transistors T1 of pnp-type and T2 of npn-type, mounted head-to-tail, the collector of one being connected to the base of the other, while the emitters of the two transistors T1, T2 are respectively connected to the supply terminal Vdd and to the ground of the circuit. The emitter-base junction of the transistor T1 is formed by the association of the P+-doped 4 and N−-doped 2 regions, whereas the collector-base junction of this transistor is formed by the association of the P−-doped substrate 1 and of the N−-doped region 2. The supply terminal Vdd of the circuit is therefore connected to the emitter of the transistor T1, and linked to the base of this transistor through a resistor RN− representing the resistance of the well 2. The base-emitter junction of the transistor T2 is formed by the association of the substrate 1 and of the N+-doped region 7 linked to the ground, while the base-collector junction of this transistor is formed by the association of the substrate 1 and of the region 2. The ground is therefore connected to the base of the transistor T2, and linked to the emitter of this transistor through a resistor RP− representing the resistance of the substrate 1.
The parasitic thyristor can be triggered by an overvoltage applied to the power supply of the integrated circuit, a negative voltage or an overvoltage applied to an input and/or output terminal of the integrated circuit, a current injection into an input or output terminal of the integrated circuit, or even by radiations of particles. This triggering produces a strong inrush current between the supply terminals of the integrated circuit, that can cause the destruction of the integrated circuit.
The specifications of integrated circuits require a minimum injected current, for example 100 mA at the maximum operating temperature (generally between 70 and 150° C.).
The sensitivity of an integrated circuit to the latch-up can be measured by injecting a current into an input or output pin of the integrated circuit, while the latter is powered normally, by detecting an over-consumption of current in the power supply, that can be more or less sudden, and by measuring the intensity of the current injected upon the appearance of the over-consumption. If the over-consumption detected stops at the same time as the current injection, the latch-up is said to be temporary. If, on the contrary, this over-consumption remains even after the current injection has stopped, the latch-up is said to be permanent. A circuit is considered insensitive to latch-up if the latter is only temporary or if a permanent latch-up only appears with an injected current having a high intensity.
There are several techniques for reducing the sensitivity of the components to latch-up, i.e., for reducing the performances of the parasitic thyristor and the value of the resistors RN− and RP− of the base of the two parasitic transistors T1, T2.
A first technique involves applying specific routing rules, and particularly adding many N and P bias regions, such as the regions 5, 6 in FIG. 1, and increasing the distance between the P- and N-channel MOS transistors. This technique runs counter to the miniaturization of integrated circuits.
Another technique involves using epitaxial substrates, so as to reduce the base resistance of one of the two parasitic transistors, i.e., in the example in FIG. 1, the resistor RP− of the base of the transistor T2. This technique involves using more expensive silicon wafers.
The base resistance of the transistors T1, T2 can also be reduced using wells made deep in the substrate and highly doped. This technique also contributes to increasing the manufacturing costs, due to the fact that it requires adding or modifying several manufacturing masks of the integrated circuit, and increases the number of manufacturing steps.
In addition, the techniques presented above are not always infallible.